Conventionally, display devices having an image capturing function have been proposed. Such display devices are provided with light detecting elements such as photodiodes, for example, in pixels, and can thereby capture an image of an object approaching to a display. These display devices having the image capturing function are to be used for a two-way communication display device or for a display device having a touch panel function.
In a conventional display device having an image capturing function, when known components such as signal lines, scan lines, TFTs (Thin Film Transistors), and pixel electrodes are formed on an active matrix substrate by a semiconductor process, photodiodes are simultaneously formed in pixels. Such a conventional display device having the image capturing function is disclosed in Japanese Patent Application Laid-Open Publication No. 2009-135185 and the like, for example.
The display device disclosed in the above Patent Document is provided with optical sensor elements having a so-called PIN thin film diode structure. FIG. 12 is a cross-sectional view showing a configuration of an optical sensor element disclosed in the above Patent Document. As shown in FIG. 12, in a conventional optical sensor element S disclosed in the above Patent Document, a first control electrode G1, which is made of a light reflective material such as aluminum, for example, is formed on a substrate 91. A gate insulating film 95 is disposed to cover the first control electrode G1. On the gate insulating film 95, a semiconductor layer 97, which is made of polysilicon, oxide semiconductor, or the like, is patterned and formed so as to cross over the first control electrode G1. The semiconductor layer 97 has a p-type region 97p and an n-type region 97n, and a light receiving section (i-type region) 97i is disposed therebetween.
An interlayer insulating film 99, which is made of a light transmissive material, is disposed to cover the semiconductor layer 97. On the interlayer insulating film 99, respective wiring lines 101, which are connected to the p-type region 97p and the n-type region 97n through connection holes, are disposed. A planarizing insulating film 103, which is made of a light transmissive material, is disposed on the interlayer insulating film 99, covering the respective wiring lines 101. In the planarizing insulating film 103, an opening 103a, which is a wide opening above the light receiving section 97i and has the interlayer insulating film 99 as a bottom surface, is formed.
On the planarizing insulating film 103, a second control electrode G2 is disposed so as to face the light receiving section 97i through the interlayer insulating film 99 at the bottom of the opening 103a. This way, on the respective sides of the semiconductor layer 97, the first control electrode G1 and the second control electrode G2 are disposed so as to sandwich the i-type region 97i through the gate insulating film 95 and the interlayer insulating film 99, respectively. The first control electrode G1 and the second control electrode G2 are wired so as not to be electrically connected to each other.
In this conventional configuration, pairs of holes and electrons generated by receiving light at the i-type region can be separated in a film thickness direction in the i-type region by applying different potentials to the first control electrode G1 and to the second control electrode G2, respectively. As a result, the holes can move to the anode (p-type region) direction and the electrons can move to the cathode (n-type region) direction while separating the holes and the electrons in a film thickness direction in the i-type region. As a result, the pairs of the holes and the electrons generated by incident light become less likely to be recombined while moving inside the i-type region, thereby improving efficiency in obtaining a current.
However, in the conventional configuration disclosed in Japanese Patent Application Laid-Open Publication No. 2009-135185 described above, as shown in FIG. 12, wiring lines 101p and 101n respectively connected to the p-type region 97p and the n-type region 97n are disposed on the same layer as and adjacently to the second control electrode G2 placed on the bottom of the opening 103a. This may cause leakage between the wiring lines 101p and 101n and the second control electrode G2 as a result of a wiring defect, entry of a foreign object, or the like occurring in a manufacturing process.